The semiconductor industry continuously searches for ways to reduce the cost per wafer processed. Several factors that affect processing costs are the costs associated with maintaining a clean room environment; equipment costs, including high precision wafer handling equipment; labor costs and the cost associated with non-value added time such as the time required for wafer transport between process chambers. Wafer costs can be reduced significantly by reducing the footprint of equipment requiring a clean room environment and by reducing the need for expensive multi-axis wafer handlers. Further reductions in wafer cost are achieved by reducing the time required to transfer wafers between a wafer carrier and a process chamber. Therefore the semiconductor fabrication industry continuously seeks improved fabrication tool configurations so as to reduce the fabrication tool's footprint, and so as to reduce the cost of fabrication tool components by simplifying the wafer transfer process.
Accordingly a need exists for a method and apparatus that, in a reduced footprint configuration, speeds and simplifies wafer transfer both within a given fabrication tool and within a collection of fabrication tools.